[  275.070926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest2-odd-counter-did-not-increment-on-overflow-if-disabled RESULT=fail>
pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest2-odd-counter-did-not-increment-on-overflow-if-disabled fail

[  274.796577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-on-even-and-odd-counters RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-on-even-and-odd-counters fail

[  274.721794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-wrapped RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-wrapped fail

[  274.668932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-recorded-for-chained-incr-2 RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-recorded-for-chained-incr-2 fail

[  274.607975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-set-to-2 RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-set-to-2 fail

pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-Odd-counter-wrapped fail

pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-expect-overflow-interrupt-on-even-and-odd-counter fail

[  278.229590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gicv2-mmio-up-gicv2-mmio-IPRIORITYR-accesses-beyond-limit-RAZWI RESULT=pass>
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-expect-overflow-interrupt fail
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-expect-overflow-interrupt-on-even-and-odd-counter fail

[  275.804320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-overflow-interrupts-expected-on-0-and-1 RESULT=fail>
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-overflow-interrupts-expected-on-0-and-1 fail

[  275.536962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest6-overflow-is-expected-on-counter-0 RESULT=fail>
pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest6-overflow-is-expected-on-counter-0 fail

[  275.478640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest5-32b-64b-CHAIN-counter-incremented-and-overflow RESULT=fail>
pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest5-32b-64b-CHAIN-counter-incremented-and-overflow fail

[  274.553920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-recorded-for-chained-incr-1 RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-recorded-for-chained-incr-1 fail

[  275.423317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest4-CHAIN-counter-enabled-CHAIN-counter-was-incremented-and-overflow RESULT=fail>
pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest4-CHAIN-counter-enabled-CHAIN-counter-was-incremented-and-overflow fail

[  275.231819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest3-should-have-triggered-an-overflow-on-0 RESULT=fail>
pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest3-should-have-triggered-an-overflow-on-0 fail

[  274.480271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-incremented RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-incremented fail

[  273.757833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-mem-access-pmu-pmu-mem-access-32-bit-overflows-Ran-20-mem-accesses-with-expected-overflows-on-both-counters RESULT=fail>
pmu-mem-access-pmu-pmu-mem-access-32-bit-overflows-Ran-20-mem-accesses-with-expected-overflows-on-both-counters fail

[  273.701713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-mem-access-pmu-pmu-mem-access-32-bit-overflows-Ran-20-mem-accesses RESULT=fail>
pmu-mem-access-pmu-pmu-mem-access-32-bit-overflows-Ran-20-mem-accesses fail
pmu-mem-access-pmu-pmu-mem-access-32-bit-overflows-Ran-20-mem-accesses-with-expected-overflows-on-both-counters fail

[  273.588490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-basic-event-count-pmu-pmu-basic-event-count-32-bit-overflows-check-overflow-happened-on-0-only RESULT=fail>
pmu-basic-event-count-pmu-pmu-basic-event-count-32-bit-overflows-check-overflow-happened-on-0-only fail

[  272.757489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-cycle-counter-pmu-cycle-counter-Cycleinstruction-ratio RESULT=fail>
pmu-cycle-counter-pmu-cycle-counter-Cycleinstruction-ratio fail

[  272.675245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-cycle-counter-pmu-cycle-counter-Monotonically-increasing-cycle-count RESULT=fail>
pmu-cycle-counter-pmu-cycle-counter-Monotonically-increasing-cycle-count fail