<8>[ 1224.987922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=micro-bench-timeout-duration90s RESULT=fail>
micro-bench-timeout-duration90s fail

<8>[ 1224.271980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=timer-ptimer-busy-loop-interrupt-signal-pending RESULT=fail>
timer-ptimer-busy-loop-interrupt-signal-pending fail

<8>[ 1223.908033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=timer-ptimer-busy-loop-latency-within-10-ms RESULT=fail>
timer-ptimer-busy-loop-latency-within-10-ms fail

<8>[ 1219.909912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-on-even-and-odd-counters RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-on-even-and-odd-counters fail

<8>[ 1219.787881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-wrapped RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-wrapped fail

pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-recorded-for-chained-incr-2 fail

<8>[ 1219.545799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-set-to-2 RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-set-to-2 fail

<8>[ 1219.421430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-recorded-for-chained-incr-1 RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-recorded-for-chained-incr-1 fail

<8>[ 1219.300456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-incremented RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-incremented fail

<8>[ 1217.117588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-event-introspection-pmu-pmu-event-introspection-Check-required-events-are-implemented RESULT=fail>
pmu-event-introspection-pmu-pmu-event-introspection-Check-required-events-are-implemented fail

<8>[ 1216.995981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-cycle-counter-pmu-cycle-counter-Cycleinstruction-ratio RESULT=fail>
pmu-cycle-counter-pmu-cycle-counter-Cycleinstruction-ratio fail

<8>[ 1216.866005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-cycle-counter-pmu-cycle-counter-Monotonically-increasing-cycle-count RESULT=fail>
pmu-cycle-counter-pmu-cycle-counter-Monotonically-increasing-cycle-count fail