[ 1482.269127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest6-overflow-is-expected-on-counter-0 RESULT=fail>
pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest6-overflow-is-expected-on-counter-0 fail

[ 1482.120176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest5-32b-64b-CHAIN-counter-incremented-and-overflow RESULT=fail>
pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest5-32b-64b-CHAIN-counter-incremented-and-overflow fail

[ 1490.282751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=timer-ptimer-busy-loop-interrupt-signal-not-pending RESULT=fail>
timer-ptimer-busy-loop-interrupt-signal-not-pending fail

[ 1489.838908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=timer-ptimer-busy-loop-interrupt-signal-pending RESULT=fail>
timer-ptimer-busy-loop-interrupt-signal-pending fail

[ 1489.397832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=timer-ptimer-busy-loop-latency-within-10-ms RESULT=fail>
timer-ptimer-busy-loop-latency-within-10-ms fail

[ 1483.925912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-64-bit-overflows-expect-overflow-interrupt-on-even-counter RESULT=fail>
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-64-bit-overflows-expect-overflow-interrupt-on-even-counter fail

[ 1483.772006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-64-bit-overflows-expect-overflow-interrupt RESULT=fail>
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-64-bit-overflows-expect-overflow-interrupt fail
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-64-bit-overflows-expect-overflow-interrupt-on-even-counter fail

[ 1483.624009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-64-bit-overflows-overflow-interrupts-expected-on-0-and-1 RESULT=fail>
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-64-bit-overflows-overflow-interrupts-expected-on-0-and-1 fail

[ 1483.169124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-Odd-counter-wrapped RESULT=fail>
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-Odd-counter-wrapped fail

[ 1483.021333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-expect-overflow-interrupt-on-even-and-odd-counter RESULT=fail>
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-expect-overflow-interrupt-on-even-and-odd-counter fail

[ 1482.869604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-expect-overflow-interrupt RESULT=fail>
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-expect-overflow-interrupt fail
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-expect-overflow-interrupt-on-even-and-odd-counter fail

[ 1482.718727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-overflow-interrupts-expected-on-0-and-1 RESULT=fail>
pmu-overflow-interrupt-pmu-pmu-overflow-interrupt-32-bit-overflows-overflow-interrupts-expected-on-0-and-1 fail

(no logs available)

[ 1481.969479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest4-CHAIN-counter-enabled-CHAIN-counter-was-incremented-and-overflow RESULT=fail>
pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest4-CHAIN-counter-enabled-CHAIN-counter-was-incremented-and-overflow fail

[ 1481.668388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest3-should-have-triggered-an-overflow-on-0 RESULT=fail>
pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest3-should-have-triggered-an-overflow-on-0 fail

[ 1481.518882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest2-odd-counter-did-not-increment-on-overflow-if-disabled RESULT=fail>
pmu-chain-promotion-pmu-pmu-chain-promotion-32-bit-overflows-subtest2-odd-counter-did-not-increment-on-overflow-if-disabled fail

[ 1480.915649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-on-even-and-odd-counters RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-on-even-and-odd-counters fail

[ 1480.763935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-wrapped RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-wrapped fail

[ 1480.616443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-recorded-for-chained-incr-2 RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-recorded-for-chained-incr-2 fail

[ 1480.463182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-set-to-2 RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-set-to-2 fail

[ 1480.312704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-recorded-for-chained-incr-1 RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-overflow-recorded-for-chained-incr-1 fail

[ 1480.163003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-incremented RESULT=fail>
pmu-chained-counters-pmu-pmu-chained-counters-32-bit-overflows-CHAIN-counter-1-incremented fail

[ 1478.520577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-mem-access-pmu-pmu-mem-access-64-bit-overflows-Ran-20-mem-accesses-with-expected-overflows-on-both-counters RESULT=fail>
pmu-mem-access-pmu-pmu-mem-access-64-bit-overflows-Ran-20-mem-accesses-with-expected-overflows-on-both-counters fail

[ 1478.371993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-mem-access-pmu-pmu-mem-access-64-bit-overflows-Ran-20-mem-accesses RESULT=fail>
pmu-mem-access-pmu-pmu-mem-access-64-bit-overflows-Ran-20-mem-accesses fail
pmu-mem-access-pmu-pmu-mem-access-64-bit-overflows-Ran-20-mem-accesses-with-expected-overflows-on-both-counters fail

[ 1478.223173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-mem-access-pmu-pmu-mem-access-32-bit-overflows-Ran-20-mem-accesses-with-expected-overflows-on-both-counters RESULT=fail>
pmu-mem-access-pmu-pmu-mem-access-32-bit-overflows-Ran-20-mem-accesses-with-expected-overflows-on-both-counters fail

[ 1478.072667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-mem-access-pmu-pmu-mem-access-32-bit-overflows-Ran-20-mem-accesses RESULT=fail>
pmu-mem-access-pmu-pmu-mem-access-32-bit-overflows-Ran-20-mem-accesses fail
pmu-mem-access-pmu-pmu-mem-access-32-bit-overflows-Ran-20-mem-accesses-with-expected-overflows-on-both-counters fail

[ 1477.923380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-basic-event-count-pmu-pmu-basic-event-count-64-bit-overflows-check-overflow-happened-on-0-only RESULT=fail>
pmu-basic-event-count-pmu-pmu-basic-event-count-64-bit-overflows-check-overflow-happened-on-0-only fail

[ 1476.418629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-basic-event-count-pmu-pmu-basic-event-count-32-bit-overflows-check-overflow-happened-on-0-only RESULT=fail>
pmu-basic-event-count-pmu-pmu-basic-event-count-32-bit-overflows-check-overflow-happened-on-0-only fail

[ 1474.318696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-cycle-counter-pmu-cycle-counter-Cycleinstruction-ratio RESULT=fail>
pmu-cycle-counter-pmu-cycle-counter-Cycleinstruction-ratio fail

[ 1474.172014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pmu-cycle-counter-pmu-cycle-counter-Monotonically-increasing-cycle-count RESULT=fail>
pmu-cycle-counter-pmu-cycle-counter-Monotonically-increasing-cycle-count fail

(no logs available)

(no logs available)

(no logs available)